Ruggedness of Integrated VDMOS Transistors Under TLP Stress

The ruggedness of integrated vertical DMOS transistors under transmission line pulsing stress is experimentally investigated at current levels close to the thermal failure current. In addition to the parasitic vertical bipolar closest to the n-sinker contact, the lateral n-p-n transistor with the p-type junction termination as a base also goes into avalanche and supports the total current. As such, the total heat generation in the transistor is shared over a larger cross section, reducing the peak temperature. Along the device width, multiple traveling current filaments are observed; the speed of each individual filament is decreasing with the stress current. A model to predict the normalized thermal failure current I
_tf
as a function of the device width is proposed. It is shown that I
_tf
follows a ~W
^-0.5
dependence