FPGA Implementation of FastICA based on Floating-Point Arithmetic Design for Real-Time Blind Source Separation

Independent component analysis (ICA) is usually used for blind source separation (BSS), and the FastICA algorithm separates the independent sources from their mixtures by measuring nongaussianity using Kurtosis. In this paper, the field programmable gate array (FPGA) implementation of FastICA for real-time signal process is proposed and the sample rate of 192 kHz is reached under the presented architecture. The floating-point arithmetic design provides better accuracy and higher dynamic performance than fixed-point design for implementation of digital signal processing algorithm. The FPGA design is based on a hierarchical concept, and the experimental results of the design are presented.