Selective MBE of High-Quality Ge on Si Covered with SiO2

A high-quality Ge epilayer on Si has emerged as a viable method to integrate III-V optoelectronics and to achieve high carrier mobility than conventional Si-based CMOS devices. The epilayer quality is often measured by the density of threading dislocations that adversely impact the carrier transport. A number of strategies have been developed in recent years to reduce the threading dislocation density in Ge epilayers grown on Si. These strategies include multiple post-growth annealing, liquid-phase epitaxy, epitaxial necking, and graded SiGe layers. In search of a relatively simple and low-temperature growth technique, we have previously demonstrated Ge "touchdown" on Si, where high-quality Ge is grown epitaxially on Si covered with a thin layer (~ 1.2 nm) of chemically grown SiO
₂
. Herein, we focus on the unique surface chemistry involving Ge, SiO
₂
, and Si that gives rise to the formation of approximately 7-nm-wide windows in the SiO
₂
layer and selective growth of Ge on exposed Si rather than on SiO
₂