VLSI design of a bit-serial word-parallel sorter

The design implementation of a sequential circuit which compares and sorts eight words simultaneously is presented. Each word is an unsigned integer of K bits, where K can be any positive integer. The words are fed into the sorter starting with the most significant bit of each word. On each clock pulse one bit from each word is received by the sorter and they are routed to their proper destination. The sorter is implemented using complementary metal-oxide-silicon (CMOS) technology.<
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