Synapse-X: a general-purpose neurocomputer architecture

A neurocomputer architecture is described which features the following characteristics: the compute-bound elementary operations are extracted from the set of neural algorithms; the elementary operations are executed by a specific VLSI neural signal processor MA16, and noncompute-bound operations by commercially available digital signal processors (DSPs) or microprocessors; the fine-grain systolic chip architecture is extensible to the board level as one- or two-dimensional systolic arrays of MA16s; each MA16 is provided with its own off-chip weight memory as well as template memory; it has systolic communication and control architecture for the array and the weight memory; it has VME and SBus interfaces; a neural algorithm programming language specifies the neural algorithms in terms of a sequence of elementary operations and their optional concatenations with DSP or host operations; and a cross-compiler translates nAPL into the machine language of the neurocomputer. The proposed architecture, SYNAPSE-1, can be considered a research instrument as well as a design platform for working out application-specific neural system architectures in terms of dedicated software and hardware.<
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