Design Of Decimation Filter For Multibit Sigmadelta Modulator With Two-step Quantization

This paper describes steps involved in a VHDL design of digital decimation filter for multibit sigma-delta (SigmaDelta) modulator. Parameters of decimation filter are derived from the specification of the multibit SigmaDelta modulator with two-step quantization architecture. Using Matlab tool it is possible to find the filter order, the required quantization level for the coefficients and their values. Finally, by analyzing the design, we can find an efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The design is programmed and tested on a Xilinx FPGA -Spartan 3 XC3S200-5FT256