An Area-Efficient Variable Length Decoder IP Core Design for MPEG-$hbox 1/2/4$Video Coding Applications

This paper proposes an area-efficient variable length decoder (VLD) IP core design for MPEG-
$hbox 1/2/4$
video coding applications. The proposed IP core exploits the parallel numerical matching in the MPEG-
$hbox 1/2/4$
entropy decoding to achieve high data throughput rate in terms of limited hardware cost. This feature not only improves the performance of VLD, but also facilitates reducing the power consumption through lowering down the supply voltage while maintaining enough data throughput rate. Moreover, we propose a partial combinational component enabling approach for minimizing the power consumption of the proposed design. Based on 0.18-
$mu$
m CMOS technology, the implementation results show that the proposed IP core operates at 125-MHz clock frequency with the cost of 13 105 gates. In addition, the power consumption of the proposed design reaches 163.4
$mu$
W operated at 12.5 MHz with 0.9-V supply voltage, which is fast enough for MPEG-1/2/4 real-time decoding on 4CIF video@30 Hz. Compared to the existing designs, the proposed IP core possesses both higher data throughput and less hardware cost.