A 10b 170MS/s CMOS Pipelined ADC Featuring 84dB SFDR without Calibration

A 0.85mm
²
3.3V 10b 170MS/s CMOS pipelined ADC using opamp-sharing technique in a 0.35mum/0.18mum CMOS process is presented. The overhead of the opamp-sharing scheme is significantly reduced using 0.18mum-long devices as sampling switches and local regulators providing the switch drivers' supply. With a 10MHz input signal, the ADC achieves 83.8dB SFDR and 9.36ENOB at 171MS/s. Better than 9.26ENOB are maintained for inputs up to 100MHz consuming 180mW at 3.3V