Self-Repairing SRAM for Reducing Parametric Failures in Nanoscaled Memory

We present a self-repairing SRAM to reduce parametric failures using an on-chip leakage sensor and application of proper body bias. Simulations in a predictive 70nm technology show 5-40% (depending on inter-die Vt variation) improvement in SRAM yield. A test-chip is fabricated and measured in 0.13 mum CMOS to demonstrate operation of the self-repair system