RTA-Driven Intra-Die Variations in Stage Delay, and Parametric Sensitivities for 65nm Technology

We report, for the first time, a detailed study of intra-die variation (IDV) of CMOS inverter delay for the 65nm technology, driven by mm-scale variations of rapid thermal annealing (RTA). We find that variation in V
_T
and R
_EXT
accounts for most of the IDV in delay and leakage and is modulated by lamp RTA ramp rate. We show a good correlation of inverter delay to mm-scale variation in the predicted reflectivity of the device pattern densities