55nm CMOS Technology for Low Standby Power/Generic Applications Deploying the Combination of Gate Work Function Control by HfSiON and Stress-Induced Mobility Enhancement

A 55nm node low standby power/generic CMOS technology is demonstrated. The transistor deploys the combination of high-k gate dielectric film and process-induced stress technologies. It features high drive currents with low leakage, wide coverage of transistor performance and process simplicity. I
_on
of 525/295 μA/μm at I
_on
of 20 μA/μm and I
_on
of 780/400 μA/μm at I
_off
of 3 nA/μm with supply voltage of 1.2 V have been achieved. A leading-edge ArF immersion lithography has been utilized for fine-pitch design rules such as L/S of 160 nm for metal 1 layer. A 0.432 μm
²
SRAM cell shows a sufficient SNM of 130 mV at supply voltage of 0.8 V