Theory and Implementation of a Computationally Efficient Decimation Filter for Power-Aware Embedded Systems

As analog-to-digital converters become faster, this will allow them to become closer to their intended sensor. This will foster an environment that will continue to allow a paradigm shift in which digital systems replace analog ones, thus mitigating many nonideal effects, lowering costs, and providing more compact computational platforms. In parallel with this trend, the importance of decimation filters will continue to expand, as the high-speed data will need to be downsampled prior to ingestion by a decision-making element, such as a digital signal processor running constant false alarm rate (CFAR) algorithms, neural networks, and the like. Ideally, these decimation filters should have as much stopband attenuation as possible and should not be hindered by timing bottlenecks. However, on a fixed-point processor, like a field-programmable gate array (FPGA), finite word-length effects are in opposition to this goal. To break this nexus, this paper employs a revolutionary integerization technique based on multidimensional continued fractions strategically coupled with an efficient multiplierless architecture design strategy. Multidimensional continued fractions have been known within the mathematical community for some time, which include the popular Furtwangler algorithm and the ordered Jacobi-Perron algorithm, but have been left unexplored in the engineering community until recently. Simultaneous rational representations (SRRs) are another member of the multidimensional continued fraction family and are employed here to create fixed integer transforms with computationally optimal representations. In addition, this paper also focuses on hardware implementations in low-cost FPGAs or application-specific integrated circuits, which benefit from multiplierless implementation to save hardware real estate. From a computational perspective, carefully choosing how to represent the coefficients of a transform may have dramatic effects on how many operations are consumed to implement it. In a low-order example, the number seven may be expressed as 2
³
-2
⁰
or 2
²
+2
¹
+2
⁰
. This concept coupled with SRRs is explored in this paper to yield low-power high-speed implementations for embedded systems