An Analytical Approach for Quantifying Clock Jitter Effects in Continuous-Time Sigma–Delta Modulators

Continuous-time sigma–delta modulators (CTSDMs) may suffer severe performance degradation from the timing error in a quantizer clock. We present an analytical approach to quantify the performance loss due to clock jitter in a CTSDM. Unlike many prior works that model the timing error of clocks as additive white Gaussian phase noise, we propose a jitter model that exhibits an auto-regression form, so we term it auto regressive (AR) jitter. This AR jitter model shows exactly the same jitter behavior as that of a clock generated by practical phase-locked loops. Based on this AR jitter model, we establish an analytical approach to examine the intricate effects of clock uncertainty on CTSDM system performance. We demonstrate the validity of the proposed analytical method by showing its excellent agreement with simulation results. The analytical method enables a profound insight into the problem of how clock jitter degrades the system performance and also provides a guideline on how to minimize the detrimental effects of clock jitter.