A 2Gb/s/pin 512Mb Graphics DRAM with NoiseReduction Techniques

A 512Mb DRAM operates up to a data-rate of 2Gb/s/pin. It employs an averaging pad-driver design which reduces simultaneous switching noise to one third of a conventional design. Resistive damping elements eliminate the level degradation of the receivers caused by an oscillation of the on-chip ground. A technique for cancelling line-to-line coupling noise is also described