The VLSI design of de-interlacing with scene change detection

This paper presents an efficient video de-interlacing technique with scene change detection and its VLSI architecture design. Scene changes happen quite often in film broadcasting and they tend to destabilize the quality of performance such as jagged effect, blurred effect, and artifacts effect, while de-interlacing technique is utilized. Therefore, the issue of scene change needs to be addressed with de-interlacing process. In the proposed method, de-interlacing begins with scene change detection, which is to ensure that the interfield information is used correctly. To improve the quality of de-interlacing, the factors of scene change are taken into account when de-interlacing techniques are applied. Besides, based on our method, the high speed VLSI architecture has been designed and implemented. And the frequency of the chip is 110MHz that it could be real-time processing for HDTV.