A 7.5mW, 11-bit continuous-time sigma-delta A/D converter for WLAN applications

A third-order continuous-time DeltaSigma analog-to-digital converter is designed for the conversion of an input signal bandwidth of 10MHz. Design optimization towards minimal power consumption is demonstrated for the high-speed, low-power building blocks of the modulator. The presented converter achieves a dynamic range of 72dB and a signal-to-noise-and-distortion-ratio of 66dB. The modulator consumes 7.5mW. It is integrated in a 0.18mum standard CMOS technology and occupies an area of 1.65mm
²