Low-power 6-bit flash ADC for high-speed data converters architectures

The design of low-power, medium resolution flash converter is presented. The goal is to provide a basic cell with state-of-the art figure of merit thus permitting low-power data converter architectures with a more flexible use of flash ADC cells. The designed 6-bit flash uses interpolation and V/I converters that operate as preamplifier stage of latches. Circuit simulations show a figure of merit as low as 1.2 pj/conv-lev at 100-MS/s sampling frequency and 3.3-V analog supply voltage