An efficient adaptive interlace-to-progressive scan conversion scheme and hardware implementation

The digital television (DTV) technology becomes widely available and the need for a good interlace-to-progressive conversion (IPC) algorithm becomes more inevitable. In this paper, a new IPC scheme is proposed, which combines several existing techniques and is suitable for hardware implementation. The proposed scheme consists of three components: a spatial linear pre-filter, a motion estimator, and a three stage adaptive recursive (3SAR) filter. The proposed adaptive filter improves the performance of the system without requiring complex hardware design. The computer simulations and real-time FPGA/ASIC implementation demonstrate the efficiency and effectiveness of the proposed scheme in hardware applications