A 10-/spl mu/W digital signal processor with adaptive-SNR monitoring for a sub-1V digital hearing aid

An ultra low-power digital signal processor (DSP) is proposed for the digital hearing aid. The DSP has a SNR monitor to vary its internal clock frequency in accordance with the input signal level. Digital filters use hardwired barrel shifters in place of multipliers, and a parameter ROM provides filter parameters. The clock generator consumes only 1 /spl mu/W at sub-1V. The DSP consumes only 10 /spl mu/W at 0.9-V single supply, and occupies 0.3 mm/sup 2/ with gate count of 10k using 0.18-/spl mu/m CMOS process.