A CMOS integrated linear voltage-to-pulse-delay-time converter for time based analog-to-digital converters

A novel 0.13mum CMOS integrated linear voltage to pulse delay time converter (VTC) is proposed. The VTC architecture uses current starved inverters where the inverter delay versus input voltage characteristic is linearized by using several parallel current starving devices with different gate bias voltages and different amounts of source degeneration. The VTC operates at a clock frequency of up to 500 MHz. Input voltage signals of up to 2 GHz can be converted to pulse time delays by using several VTC's in parallel. Since the voltage to time conversion is essentially done with a single inverter stage no sample-and-hold is needed for the input voltage. The VTC can be used in combination with a time-to-digital converter (TDC) to build a simple high speed, low power, time based analog-to-digital converter (ADC) that consumes very little chip area