Representing the Effect of Instruction Prefetch in a Microprocessor Performance Model

The implementation of variable addressing and block structure has a substantial influence on the global system performance. One model dederibes this influence as a product of program statistical, architectural and technological parameters, but only for sequential processors. In this correspondence we adapt this model to processors with an instrution prefetch pipeline. An upper and lower bound for the performance measure is obtained, using a best/worst case analysis. The influence of the memory speed on the performance is also determined.