Shallow junctions in silicon via low thermal budget processing

The paper summarises recent findings concerning the fabrication of ultra-shallow junctions in silicon for future generations of CMOS devices. In particular we concentrate on vacancy engineering to achieve carrier concentrations of 5-6times10
²⁰
cm
^-3
for boron in silicon without diffusion and report for the first time preliminary data for antimony implants into strained silicon in which even higher carrier concentrations were obtained. All of this can be produced at temperatures below 800degC for annealing times of 10 seconds, without the need for spike annealing, fast ramp rates or laser processing