20V-40V Symmetrical Vertical Trench nMOS (SVT MOS) design for display driver ICs

This paper presents a novel 20V/40V symmetrical vertical trench MOS (SVT MOS) having both drain extension and gate realized in vertical direction respect to the silicon surface. Using silicon depth to realize the gate and to withstand high voltage, carefully designing doping implants and realizing a vertical field oxide, it was possible to reduce more than 60% the device pitch (i.e. spacing between half drain contact and half source contact) maintaining the same performance of equivalent lateral device