Hardware architecture design for explicit model predictive control

Solutions to constrained linear and hybrid model predictive control (MPC) can be explicitly characterized in terms of piecewise linear (PWL) state feedback control. A PWL controller is pre-computed using parametric programming, and the exact explicit MPC implementation corresponds to the evaluation of a PWL function in the control unit. It has recently been shown that such evaluation can be boosted by binary search tree data structures. We report digital hardware architecture design results for this type of PWL control, and show that explicit MPC solutions can be implemented in a standard field programmable gate array (FPGA) or an application specific integrated circuit (ASIC) with about 20 kGates leading to computation times around one microsecond per evaluation for typical applications. This facilitates implementation of constrained MPC in small-scale industrial and consumer electronics applications that are characterized by fast sampling or low production cost, such as mechatronics, MEMS, rotating machinery, power electronics, and acoustics