A New Global Interconnect Paradigm: MIM Power-Ground Plane Capacitors

Based on scaling trends observed with a model for global interconnect pitch, a new paradigm is introduced for ASICs in which power and ground planes separated by a high k dielectric are placed on-chip. This gives a 4times reduction in on-chip IR drop, reduces di/dt noise due to package inductance by 2.6times without using any transistor area for decoupling capacitors (decaps), improves clock wire latency by 5%, reduces delay of global signal wires by 23% and decreases energy per bit for global signal wires by 22%. Thus, global interconnect problems could be substantially alleviated