Thermal Cycle Reliability of 3D Chip Stacked Package Using Pb-free Solder Bumps: Parameter Study by FEM Analysis

This study is aimed at analysing the reliability of a three-dimensional (3D) chip stacked package under cyclic thermal loading. The critical areas in the 3D chip stacked package are defined with finite element modeling (FEM) based simulations to correlate the thermal cycling experiments. The 3D chip stacked package consists of two 300mum thick Si chips vertically connected with Sn-Ag-Cu solder bump joints and then assembled on a conventional FR-4 printed circuit aboard (PCB). Two thermal cycle conditions are studied, namely: -40 to 125degC and 0 to 100degC. FEM simulations indicate that in both conditions, the critical failure location is expected to be in the chip side region of the corner solder bump of the lower chip connecting the package to the PCB. Creep strain per single thermal cycle averaged over a critical damage volume; Deltaepsiv
_cr
is used as the damage parameter. Furthermore, we have investigated the possible approaches to improve the thermo-mechanical reliability for this package. The results indicate that adding an underfill or thinning Si chips will achieve lower creep strain in solder bumps. Furthermore, the stress levels in Si and Cu via in the Si chip are low. Therefore fracture of Si chips and fatigue of Cu vias is not expected under thermal cycling conditions