The architecture of the GenTest sequential test generator

GenTest is an automatic test pattern generator for sequential circuits. There are few constraints on the circuit, and scan design is not required. GenTest consists of the STG3 test generator and the DSIM differential fault simulator. The architecture of GenTest is described in detail, including the test generator, the embedded fault simulator, and the models of sequential elements used. GenTest has recently been extended to support test generation for circuits to be tested using current monitoring or I/sub DDQ/. Results of runs on the ISCAS'89 benchmarks are provided.<
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