Characterizing a VLSI standard cell library

The author describes a set of procedures for maintaining and characterizing an ASIC (application-specific integrated circuit) standard cell library. A modular set of programs that generate timing parameters and associated documentation in a well-integrated design environment has been developed. Input to the system is ideally a layout description in GDSII format; its outputs are direct interfaces to the logic simulator and a data sheet for documentation purposes which is further processed by TROFF. The advantage of the proposed approach compared to other systems is the separation of the stimuli databases from the process of parameter extraction. Another advantage is the flexibility of the approach.<
>