A pipelined 9-stage video-rate analog-to-digital converter

The authors describe a nine-stage, pipelined, video-rate, analog-to-digital converter (ADC) in a 0.9- mu m CMOS technology. At a conversion rate of 20 Msamples/s, the converter has 10-b resolution, 56-dB signal-to-noise-and-distortion ratio (SNDR) with a 100-kHz input, and 54-dB SNDR with a 5-MHz input. It occupies 9.3 mm/sup 2/ and dissipates 300 mW. The key innovation in this ADC is the improved correction algorithm, which requires one fewer comparator per stage than used in traditional architectures.<
>