A Fast Locking PLL With Phase Error Detector

A fast locking phase-locked loops (PLL) with a phase error detector (PED) circuit is presented. The PED circuit is composed of a dual-slop phase frequency detector and a charge-pump characteristic. The proposed architecture can efficiently reduce both the power dissipation and the acquisition time of the PLL while the loop stability remains unchanged. The proposed PLL is designed in a standard CMOS 0.35μm technology through a 3.3V power supply. The simulation results show that the settling time of the proposed PLL is below 150ns. There is over 50% reduction of the locked time in comparison with the conventional PLLs. The power consumption is 18.5mW at 2.4GHz.