High-performance deep-submicrometer Si MOSFETs using vertical doping engineering

Vertical doping engineering was used to implement deep-submicrometer Si MOS devices with excellent room-temperature turn-off and turn-on characteristics, circumventing the conventional scaling obstacles. The vertically engineered doping profile was realized using a 90-keV 1*10/sup 13/ cm/sup -2/ BF/sub 2//sup +/ implant for NMOS and a 100-keV 1*10/sup 13/ cm/sup -2/ As/sup +/ implant for PMOS, and minimal subsequent thermal treatment, for devices with 0.15- mu m minimum effective channel length, 4.0-nm thermally grown gate oxides, and self-aligned silicides on source, drain, and poly-gate. Room-temperature measurements show transconductances of 570/230 mu S/ mu m, threshold voltages of 0.45/-0.3 V, and subthreshold slopes of 84/88 mV/dec for NMOS/PMOS devices with a power supply voltage of 1.5 V.