Circuit modeling of bipolar transistors for BiCMOS

Modeling of a worst-type bipolar transistor implemented in a BiCMOS process is examined, and an appropriate DC model is developed for circuit simulation. This model is implemented as a SPICE subcircuit with various components representing parasitics associated with the transistor. The model can be adjusted by the removal of relevant parasitics to suit other BiCMOS implementations. The worst-type transistor considered has no buried layer or epitaxy, with the CMOS well forming the collector region. This results in a large and possibly nonlinear collector resistance. A high-gain parasitic substrate transistor is also present which leads to substrate current flow during transistor saturation. Collector resistance and substrate current are analyzed, and suitable expressions for these are included in the model without modification of SPICE models. Results are presented for n-p-n transistors in an n-well CMOS process and for p-n-p transistors in a p-well process. The model is used to simulate a simple analog BiCMOS circuit, and good agreement with measured results is obtained for circuit and parasitic currents.<
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