A novel performance-driven placement based on hybrid genetic algorithm

Deep-sub-micron technology (DSM) of 0.18 micron and below enable the integration of logical circuits having more than 10 million gates. In such a DSM technology, layout design has become the most important design phase. This paper discusses a novel performance-driven placement technique. The proposed algorithm based on hybrid genetic algorithms (GA) has a two-level hierarchical structure. For selection control, new objective functions are introduced for improving power consumption, interconnect delay, wire congestion and chip area. Experimental results show improvement comparison with commercial EDA tool.