Impact of strained-Si thickness and Ge out-diffusion on gate oxide quality for strained-Si surface channel n-MOSFETs

Surface channel strained-silicon MOSFETs on relaxed Si/sub 1-x/Ge/sub x/ virtual substrates (VSs) have been established as an attractive avenue for extending Si CMOS performance as dictated by Moore's law. The performance of a surface channel Si n-MOSFET is significantly influenced by strained Si/SiO/sub 2/ interface quality. The effects of Ge content (20, 25, and 30%) in the VS and strained-Si thickness (6, 5.5, 4.7, and 3.7 nm) on the strained Si/SiO/sub 2/ interface have been investigated. The interface trap density was found to be proportional to the Ge content in the VS. Fixed oxide charge density reduces to a lower limit at higher strained-Si thickness for any Ge content in the VS, and the value increases as the strained-Si thickness is reduced. There is a high concentration of interface trap charge and fixed oxide charge present for devices with a strained-Si channel thickness below 4.7 nm. To investigate the effect of strained Si/SiO/sub 2/ interface quality on MOSFET devices fabricated using a high-temperature CMOS process, the performance of surface channel n-MOSFETs has been correlated with channel thickness. It is noted that the drain-current rapidly decreases at low gate voltages for channel thicknesses less than 4.7 nm. The performance of both MOS capacitors and MOSFETs degraded below a strained-Si thickness of 4.7 nm irrespective of the Ge content in the VS even up to 30%. TCAD simulations have been carried out to analyze the effect of strained Si/SiO/sub 2/ interface on electrical characteristics. Performance degradation in thin strained-Si channels is primarily attributed to gate oxide quality. The out-diffused Ge accumulates at the strained Si/SiO/sub 2/ interface, introducing a significant amount of interface traps and fixed oxide charges during thermal oxidation. Interface trap density and fixed oxide charge density significantly increased when the Ge concentration at the surface becomes more than 6%. This paper suggests that a minimum strained-Si layer thickness of /spl sim/ 5.0 nm is required to achieve a good strained Si/SiO/sub 2/ interface quality for surface channel strained-Si n-MOSFETs, fabricated using a high thermal budget CMOS process.