VLSI implementations of ATM buffer management

An architecture is introduced for a semi-shared buffer containing multiple FIFO (first in, first out) queues. The simple and fast FIFO stack approach is generalized to allow overlapping, leading to memory efficiencies similar to those of complex, fully shared architectures. A comparison is made of performance and VLSI implementation costs across the range of separated, semi-shared, and fully shared buffers.<
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