Design of 2.5V, 900MHz phase-locked loop (PLL) using 0.25/spl mu/m TSMC CMOS technology

In this paper, a 2.5V, operating at 900MHz phase-locked loop implemented in 0.25/spl mu/m TSMC CMOS process technology is presented. A high speed PFD is implemented using true-single-phase clock (TSPC) technique which manages to operate up to 1.1 GHz. VCO using ring oscillator with dual-delay path scheme is implemented to achieve 900MHz operation frequency with wider tuning range. The PLL manage to lock within 100ns. The PLL implementation only needs 67 transistors and consumes 23.81mW.