50% PAE 20-mA quiescent current W-CDMA power amplifier with on-chip dynamic-gain linearizer

This paper explains a power-effective linearization technique for power amplifiers (PAs) having gain-expansion characteristics. A new on-chip dynamic-gain-deviation cancellation circuit improves the adjacent-channel-leakage-power ratio (ACLR) for a W-CDMA signal by 11 dB. At a supply of 3.5 V and an output power of 26.9 dBm, a fabricated PA with a quiescent current (Iq) of 19 mA exhibited a power-added efficiency of 50%, a gain of 26 dB, and an ACLR of -40 dBc. Furthermore, when we applied this technique to a PA with Iq of only 10-mA, this PA also satisfied the W-CDMA criteria.