Through wafer copper via for silicon based SiP application

Portable electronic products demand integration of different functional chips like digital, RF and optical in a single module. Integration of multifunctional chips on silicon, organic and ceramic substrates for system in package is fast emerging technology. Presently chip level and package level stacked modules are primarily used for memory modules as presented by Val, (1994). In chip stacking technology, different die sizes are stacked in a pyramid structure or same die sizes are stacked with spacer technology as presented by Fukui et al. (2000). In package level stacking, thin packages are stacked one over the other as presented by Kripesh et al. (2005). But mass manufacturability, quick turn-around time, integrated thermal management and electrical testing are the major bottlenecks for the above technologies. In these paper, 3D stacked modules using silicon carriers that can integrate various functional devices for heterogeneous integration is investigated. The back bone of this silicon based system in package (SiP) is the fabrication of silicon carrier with through Cu via interconnects. Process development, issues and limitations of the conventional method to fabricate silicon carriers with Cu via interconnect are discussed in detail. A new low cost method for carrier wafer fabrication is also discussed. DRIE etched 8-inch silicon carriers are fabricated and Cu via hole are filled with electroplating method. Different via sizes of 300 /spl mu/m and 200 /spl mu/m are fabricated and tested. After Cu via plating, dielectrics and metal layers are deposited and prepared by lithography and metal etching process. Solder bumps are attached on the carrier to provide interconnection of stacked module. Finally 5 ultra thin test devices with daisy chain are fabricated and attached to the silicon carriers by conventional flip chip and wire bond processes, forming a 3D-SiP module. This research study focuses on a simple, low cost and time saving methods of fabricating carrier wafers with Cu plated via interconnects for 3D SiP applications.