Advanced activation and stability of ultra-shallow junctions using flash-assisted RTP

Advanced-logic device technology for the 65 nm node and beyond requires highly-activated, shallow, and abrupt dopant profiles (Int. Technol. Roadmap for Semicond., 2003). The combination of ion implantation and an advanced annealing technology is expected to provide solutions for these requirements. In contrast to spike annealing, a diffusion-less but highly activating, high-temperature, flash-assisted RTP annealing approach for the formation of ultra-shallow junctions will be demonstrated. The flash-assisted RTP technique is a promising method for achieving junction depth and sheet resistance values low enough to meet the performance specifications for the 65 nm node and beyond (Gelpey, et al., 2002, McCoy, et al., 2004). The optimal process for high activation during flash-assisted RTP involves a temperature ramp-up to an intermediate temperature between 700degC and 900degC and, once the intermediate temperature is reached, a very short, intense flash on the front side of the wafer induces a temperature jump up to 1325degC with a peak width of approximately 1.6 ms in a 100 ppm oxygen in nitrogen gaseous ambient. In this paper, we will present some of our recent p
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MOS and n
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MOS results on the fabrication of ultra-shallow junctions using flash-assisted RTP in crystalline and pre-amorphized silicon. It will be shown that such junctions are suitable for future technology generations. The measured "mechanical/electrical" sheet resistance values of the junctions are compared to Hall measurements on the same samples to gain an insight into the reliability of the destructive four-point probe (4PP) method for such extremely shallow junctions. Deactivation studies will be presented to examine the stability of the process to the required subsequent thermal processes