FPGA based DPA-resistant Unified Architecture for Signcryption

Signcryption is a cryptographic primitive supporting both confidentiality and authentication. This paper proposes a DPA-resistant unified architecture for signing, encryption and signcryption with high performance and areaefficiency. Modular exponentiation is the main operation of RSA and ECC and also the key part of implementing signcryption. A unified signed adder is proposed to address the possible method to unify the modular exponentiation on GF(p) field and GF(2p) field. Our simulation results show that the overall speed(maximum frequency of 1024 key length for RSA and 160 key length for ECC) can be increased approximately 28% of the existing design when our proposed design ported to FPGA with the utilization of 4355 CLBs.