Impact of process variation on soft error vulnerability for nanometer VLSI circuits

In this paper, the impact of process variation on-soft error vulnerability for nanometer VLSI circuits is studied. Particle strike is modeled in SPICE as a current source connected to the node of interest. Q/sub critical/ of four kinds of circuits at different technology nodes is analyzed. Our simulation result shows that process variation can make Q/sub critical/ vary from -33.5% to 81.7% compared to the case without considering process variation. Because of the exponential dependence of SER on /sub critical/, the result shows significant impact of process variation on SER. Gate length found to be the most important variability source while the influence of threshold voltage cannot be ignored.