A 10-bit 30-MS/s 50mW pipelined A/D converter

A 10-bit 30-Msample/s pipelined analog-to-digital converter is designed and implemented in a 0.6/spl mu/m CMOS technology. Sampling capacitors scaling technique is employed to reduce the power dissipation. The digital correction technique is used to relax the offset requirement of the comparators. A sample-and-hold amplifier (SHA) is also used to improve the signal-to-noise and distortion ratio (SNDR) performance and the linearity of ADC. The simulation and experiment results reveal that the ADC designed with this method achieves the SNDR of 58dB or the ENOB of 9.34 at full speed of 30MHz when input frequency is 7MHz. Furthermore, the ADC consumes only 50mW power at 5V supply voltage with a low power operational transconductance amplifier (OTA) and the dynamic comparators.