Design of low-power double-edge triggered flip-flop

A flip-flop is a bistable circuit which stores a selected logical state in response to a clock pulse and one or more data input signals. To reduce the complexity of circuit design, a large proportion of digital circuits are synchronous circuits; that is, they operate based on a clock signal. Among the more popular synchronous digital circuits are edge-triggered flip-flops. In this paper, we proposed a flip-flop which includes an upper data path responsive to the rising edge of the clock signal and a lower data path responsive to the falling edge of the clock signal, thereby allowing data to be stored on both the rising edge and the falling edge of the clock signal. Moreover, a multiplexer is used to provide data output buffering.