Post-layout parasitic verification methodology for mixed-signal designs using fast-SPICE simulators

Current sub-100 nanometer processes employ complex multilayer metallization structures with advanced dielectric materials. Closely-spaced thin, tall metal interconnects with low voltage and fast-clocking edges lead to circuit performances dominated by parasitic delays. Various issues such as noise and delay associated with cross-talk due to coupling capacitances; IR drop effects in the low power supply operating regimes; high current density causing electromigration in narrow interconnect structures; and DC path leakage currents are becoming very common effects in recent mixed-signal designs. Full-chip, post-layout simulation with extracted parasitic components is required in the design flow to accurately analyze each of these effects. Due to the presence of a large amount of parasitics, it is important to extract appropriate parasitics for the relevant process corners and perform the analysis. Fast-spice simulator-based flows are becoming prevalent due to their capacity and efficiency in handling large amounts of data. In this paper, we discuss various options available for designers using fast-spice simulators (e.g. UltraSim, NanoSim, and HSIM) for post-layout simulations, and how these options affect the end results. We have simulated the design with 2.5 million RC elements in 13 hours using a fast-spice simulator. A few examples of post-layout simulations carried out on designs will be discussed.