Layout dependence effect on high speed CMOS transistor leakage current

We investigated the layout dependence effect that is caused by different active space, Sa, on 130 nm CMOS transistors leakage current, Ioff. This layout dependence phenomenon is known as STI stress effect. The results show that when Sa changes from 5 /spl mu/m to 0.34 /spl mu/m, the NMOS Ioff decreases and the PMOS Ioff increases. The decrease of NMOS Ioff and increase of PMOS Ioff under compressive stress is similar to the trend of saturation current, Idsat but opposite the trend of linear threshold voltage, Vtlin. The layout dependence (or STI stress effect) not only affects the Vtlin and Idsat but also the Ioff of the 130 nm CMOS transistors.