Analysis of deep submicron CMOS transistor Vtlin and Idsat versus channel width

We investigate the 130nm (1.2V) and 280nm (2.5V) CMOS linear threshold voltage (Vtlin) and normalized saturation drain current (Idsat) versus channel width. Plots of Vtlin and Idsat versus channel width for different lengths are used to show the complex behavior as the channel width decreases. Both NMOS and PMOS Vtlin reach a maximum and then decrease as the width goes to W = 0.15/spl mu/m. NMOS Vtlin shows a 30% decease while PMOS Vtlin decreases 5% to 18%. We then show that the Vtlin behavior is caused by two opposite factors, shallow trench isolation (STI) y-stress effect and inverse narrow width (INW) effect. We eliminate x-stress as a factor by designing all the transistors with Sa = 10/spl mu/m. We observe that NMOS and PMOS Idsat decrease as the width decreases from 20/spl mu/m to 1/spl mu/m reaching a minimum, after that Idsat increases again. We believe this Idsat behavior is also caused by two opposite factors, STI y-stress effect and delta width, DW effect. The Idsat behavior is different for NMOS and PMOS. The STI y-stress effect is less pronounced for short channel NMOS transistors while the DW effect is weaker for short channel PMOS transistors.