Lessons in Language Design: Cost/Benefit Analysis of VHDL Features

This paper looks at the design of one successful hardware description language, VHSIC Hardware Description Language (VHDL) with a critical evaluation of particular language features. In the paper we identify features of VHDL that burden the language in terms of development time (i.e. price), performance of the implementation, and user-friendliness. We suggest a useful and instinctive tool to assess the redundancy of language features. We also give an explanation as to why such superfluous features are included in VHDL. While it is quite obvious that the restandardization process is not designed to remove features from VHDL, it is interesting, at the end of a major language redesign process, to draw lessons that can benefit language designers, implementors, and users.