A CMOS 2.4 GHz delay-locked loop based programmable frequency multiplier

A CMOS delay-locked loop based frequency multiplier is presented. The multiplication factor N/2 can be chosen according to the number of the delay cell and the cascade stage of the multiplier sub-circuit. The output frequency range is from 270 MHz to 2.4 GHz using tsmc 0.18 /spl mu/m CMOS process parameters. The power consumption is 4 mW with a 1.8 V supply. The locking time of the DLL core is 1.78 /spl mu/m at 270 MHz and 0.77 /spl mu/s at 400 MHz. The phase errors are 43.44 ps at 270 MHz and 19.55 ps at 400 MHz. The cycle-to-cycle jitter of the DLL core is 8.29 ps.