Implementation of synchronization for 2/spl times/2 MIMO WLAN systems

The proposed synchronization is designed for 2/spl times/2 MIMO OFDM WLAN systems. A novel CSIO structure is implemented to recover the carry frequency. The proposed design chiefly improves the conventional CORDIC-based structure which is used at each accumulated phase. Considering the iterative CORDIC computation, our CSIO structure only operates the CORDIC once. Moreover, the timing controller negotiates these two antenna input signals and gates the useless signal to reduce the power consumption. This architecture is simulated by UMC 0.18 /spl mu/m IP6M CMOS technology, and the CSIO function is also emulated by VirtexII XC2V1500. It provides the high precision with the area of 1.682 mm/sub 2/. The power consumption is 90.53 mW at 20 MHz.