Automatic biasing and sizing of CMOS analog integrated circuits

An automatic method is introduced to the biasing and sizing of CMOS analog ICs. First, from a netlist alike SPICE, a CMOS circuit is partitioned into sub-circuits by identifying current-loops formed by a group of transistors connected in a current bias path, beginning from the most positive voltage and finishing to the least negative one. Second, for each sub-circuit, the method calculates W and L of each transistor by assigning voltage bias levels at each node and by distribution of the current bias reference among current-loops. Some examples are given by using CMOS technology of 0.35/spl mu/m to show the suitability of the proposed method to be incorporated within an automatic synthesis tool.